The ability to test the functionality of devices in a system, and the connections between the devices, has become more important along with increased complexity of systems using one or more integrated circuit boards. While advances in board interconnect technology, such as surface mount packaging and integrated circuit (IC) gate density, have had a positive influence on the design of state-of-the-art electronic systems, they adversely affect system-level testability. The increased complexity of circuit boards makes it more difficult and costly for a manufacturer to test board designs using traditional testing techniques. One of the test areas which is critically affected by advance technologies is in-circuit testing. Conventional methods of in-circuit testing rely on the ability to physically access the board, using probing fixtures, to apply stimulus and measure response from the circuit under tests. However, as board layouts become denser, the space allocated for probing is being reduced, and in some cases, deleted altogether.
Boundary scan is the application of a partitioning scan ring at the boundary of IC designs to provide controllability and observability access via scan operations. The application of a scan path (an interconnection of one or more scan devices interconnected such that serial data can be passed between the devices) at the boundary of integrated circuit designs provides an imbedded testing capability that can overcome the test access problems associated with complex board designs. More generally, serial scan testing allows observation and control of isolated nodes attached to serially connected nodes.
In a complex system, it is desirable to partition the boards into a plurality of scan paths which may be accessed either individually or in conjunction with one another. Heretofore, in order to gain access to one of the scan paths in each board design, the primary bus master would need a number of output signals equal to the sum of the total scan paths of each board in the system. For example, in a system with N board designs, with each board having m selectable scan paths, the primary bus master must have a number of output signals equal to mN. Hence, a system with twenty boards, with each board having five individually selectable scan paths, the total number of output signals required from the primary bus master would require one hundred IC package pins, along with additional package pins for clock and data input/output signals.
Furthermore, prior art systems do not provide for an inherently fault tolerant scan path networking scheme. Thus, if an open circuit or short circuit fault condition were to occur on one of the scan paths, the operation of the entire system scan path would be disabled.
Another problem associated with the prior art is that it has not addressed the capability of allowing either a primary or remote test bus master device to select and shift data through any one of the secondary scan paths.
Therefore, a need has arisen in the industry to provide apparatus capable of selecting or deselecting secondary scan paths onto a primary scan path to customize the total length of the primary scan path for a particular scan operation. Furthermore, the apparatus should provide fault tolerance and the ability to select primary and remote test bus masters.